The DC gate bias of a field effect transistor ("FET") affects the DC and AC operating characteristics of the transistor. It is desirable that FETs which are fabricated into integrated circuits ("ICs") exhibit predetermined DC and AC operating characteristics. The power drain caused by the bias current is one of the major DC characteristics that needs to be predictable and well stabilized. The AC operating characteristics of the FETs in an IC affect circuit characteristics such as the gain of the circuit. Yet, when the FETs are fabricated, there are variations in the physical characteristics which are unavoidably introduced due to variations in the fabrication process and the fabrication material.
FIG. 1 shows typical current curves for an N-channel depletion mode FET. The curves plot the change in drain to source current ("I.sub.DS ") as a function of the drain to source voltage ("V.sub.DS "). The curves A, B, and C are for gate to source voltages ("V.sub.GS ") equal to 0 volts, -1 volt, and -2 volts, respectively. As can be seen by all three curves, at first, the I.sub.DS increases as the V.sub.DS increases. This behavior continues up to a point called the pinch off voltage ("Vpoff") of the FET. After the Vpoff, the I.sub.DS tends to level off until the breakdown voltage ("V.sub.B ") is reached. When the V.sub.DS Of the FET is between the Vpoff and the V.sub.B, the FET is operating in the saturation region. In the saturation region, the I.sub.DS is called the saturation current. In typical applications, such as a power amplifier ("PA"), an FET is biased to operate within the saturation region.
As can be seen by the curves A, B, and C in FIG. 1, the saturation current, the Vpoff and the V.sub.B of the FET are a function of the V.sub.GS. Consequently, the V.sub.GS may be used to compensate for variations in the operating characteristics generally, and the DC characteristics particularly, of an FET that may occur due to variations in the fabrication process. Variations in characteristics such as dopant concentration, uniformity of the layers making up the FET, and the length and width of the gate electrode from wafer to wafer or lot to lot may introduce variations in the operating characteristics of an FET. These variations in the operating characteristics of the FET may be manifested as a change in the Vpoff and thereby, the saturation current of the FET for a given bias condition (e.g., a fixed gate to source and drain to source voltage).
When an FET has a saturation current that deviates from a desired value for a specified V.sub.GS, the V.sub.GS may be adjusted to compensate for this variation. By appropriately adjusting ("tuning") the DC bias (e.g., the V.sub.GS) of the FET, the I.sub.DS may be adjusted back to the desired level. This can help stabilize the input and output characteristics of a circuit in which the FET is incorporated.
This adjustment can be done experimentally by measuring the input and output characteristics of a given circuit and then appropriately tuning the FET's bias to produce a desired result. The problem with this technique is that each integrated circuit may need to be individually tuned to compensate for the fabrication variations. This is a very cumbersome and time consuming task which unacceptably increases the cost of fabricating the ICs into which the FETs are incorporated. Further, additional pin outputs on the IC may be required to tune properly an IC. This may be unacceptable in applications where additional pin outputs are already limited due to other IC constraints.
In the prior art, a bias stabilization circuit allegedly may compensate for variations in a transistor's (e.g., a stabilized transistor) operating characteristics without requiring tuning. However, a practical bias circuit in a production environment should stabilize the current with respect to all the possible parameters affecting it. Depending upon the circuit implementation, these parameters could be:
(i) Vpoff variations, PA1 (ii) Resistance variations in the resistors that are typically used to control the bias current, PA1 (iii) Positive Power supply ("VDD") variations of the bias stabilization circuit, and PA1 (iv) Negative Power supply ("VGG") variations of the bias stabilization circuit. PA1 (i) Considering a PA circuit as an example, for such applications the transistor width (W) of the PA circuit (e.g., the stabilized transistor) is usually very large in relation to the bias transistor. This means that the leakage current from the stabilized transistor's gate may also be large. This can lead to a thermal runaway problem. To avoid such a situation, the bias stabilization circuit should present a relatively low output resistance to the stabilized transistor's input. PA1 (ii) In some applications, such as a PA circuit, a negative voltage is often provided for optimal operation of the circuit. This negative voltage may be generated by a switching inverter circuit. Such circuits only have a limited current sinking capability. A useful bias stabilization circuit must therefore respect this constraint as well.
Point (iv) above can be appreciated in light of the fact that in most GaAs technologies, only depletion mode devices are available. To use these devices at an optimum bias level, say for a PA, one often needs a negative power supply. Thus, the PA circuit for instance should be stabilized with respect to the process variations, such as variations in the Vpoff of the transistor and resistance variations in the bias resistors, and with respect to the system variations, such as variations in VDD and VGG of the bias circuit.
In some applications, the bias stabilization circuit may not need VDD to operate. In these cases, a ground pin may be used in the place of a positive power supply for the bias stabilization circuit as shown in U.S. Pat. No. 5,412,235 to Nakajima ("the '235 Patent") discussed in more detail below. This eliminates the need for the circuit to be stabilized with respect to the VDD. However in this case, it may not always be possible to adequately stabilize the DC bias current of the main circuit. Furthermore, in most cases at least the other three parameters are present and variations in those parameters should be compensated for by a bias stabilization circuit that is useful in practical applications.
In addition to the above four parameters, the bias stabilization circuit often has to comply with other system constraints as well. Two such possible system constraints are discussed below:
One prior art method that claims to stabilize the operating characteristics of an amplifier transistor is disclosed in the '235 Patent. The contents of the '235 Patent are incorporated herein by reference.
FIG. 2 shows a gate bias stabilization circuit 200 and an amplifier 210 as disclosed in the '235 Patent. The bias stabilization circuit 200 is comprised of an FET ("a bias transistor 110"), a resistor 114, a resistor 115, a resistor 118 and a resistor 119. The bias transistor 110 is fabricated on the same chip on which an FET ("a stabilized transistor 111") of the amplifier circuit 210 is fabricated. By this method, the fabrication process variations that affect the stabilized transistor 111 will also equivalently affect the bias transistor 110.
In the circuit disclosed in the '235 Patent, the drain (D) of the bias transistor 110 is connected to a first end of the resistor 114 and a gate (G) of the stabilized transistor 111. A second end of the resistor 114 is connected to a ground potential. A source (S) of the bias transistor 110 is connected to a first end of the resistor 115. A second end of the resistor 115 is connected to a negative power supply ("VGG") and a first side of the resistor 119. A second side of the resistor 119 is connected to a gate (G) of the bias transistor 110 and a first side of the resistor 118. A second side of the resistor 118 is connected to a ground potential.
In operation, the drain to source current ("I.sub.dpa ") of the stabilized transistor 111 may vary due to fabrication process variations (see discussion above). This change in I.sub.dpa is primarily due to a change in the Vpoff of the stabilized transistor 111. Considering these variations, if the Vpoff is more negative than a desired value due to fabrication process variations, then the drain to source current may tend to be greater than a desired value in both the bias transistor 110 (e.g., I.sub.db) and the stabilized transistor 111 (e.g, I.sub.dpa). The increased drain to source current I.sub.db in the bias transistor 110 tends to make the voltage V.sub.B, at the drain of the bias transistor 110, more negative (see equation 1 below).
To simplify the discussion it is assumed that (i) the gate leakage currents of the bias transistor 110 and the stabilized transistor 111 are negligible; (ii) the resistor 118=open and the resistor 119=short; and (iii) RL=the resistance of resistor 114. Thus, from FIG. 2: EQU V.sub.B =-I.sub.db *(RL) (1)
and, since the gate leakage currents are negligible (see assumption (i) above), a voltage (V.sub.P) at the gate of the stabilized transistor 111 is: EQU V.sub.P =V.sub.B (2)
As mentioned above, if I.sub.dpa tends to increase by .DELTA.I.sub.dpa due to a variation in the Vpoff (e.g., .DELTA. Vpoff) of the stabilized transistor 111, I.sub.db tends to increase by .DELTA.I.sub.db. This increase in I.sub.db tends to bring down the potential at the drain of the bias transistor 110 by .DELTA.V.sub.B, equal to: EQU .DELTA.V.sub.B =-(.DELTA.I.sub.db *(RL)) (3)
If EQU .DELTA.V.sub.B =.DELTA.Vpoff, (4)
the current I.sub.dpa stays constant as the effect of the Vpoff variation of the stabilized transistor 111 is counteracted by the gate voltage (V.sub.P =V.sub.B) variation in the same direction and by supposedly the same amount.
Due to this stabilization, (V.sub.P -Vpoff) stays constant causing the current I.sub.dpa to remain unaffected by the Vpoff variations. In practice, however, exact cancellation of the Vpoff variations are not possible and I.sub.dpa tends to vary to some extent. The objective of any bias stabilization circuit is to keep this variation within tolerable limits.
In equation (3), RL can be seen as a gain factor which "amplifies" a given .DELTA.I.sub.db variation to a desired .DELTA.V.sub.B that is required to cancel the Vpoff variations. Therefore, for the required "exact" or near perfect cancellation of variations in the I.sub.dpa, a specific value of RL is needed for a specific value of the nominal I.sub.db current. It should be noted that this specific value of RL may not be the same as that required to satisfy equation 1.
This is one of the main shortcomings of the device disclosed in the '235 Patent. Since the potential connected to the second side of the resistors 114 and 118 in the '235 Patent (see FIG. 2) are fixed to a ground potential (0 V), an arbitrary choice of RL is difficult to select. This is because RL also fixes the nominal DC gate potential of the stabilized transistor 111 (see equation 1) which often times is determined from other considerations, such as the required efficiency and linearity expected of a circuit such as a PA.
It can thus be difficult to select a value of RL which gives the required nominal DC bias voltage V.sub.P (see equations 1 and 2) and at the same time achieves the near perfect cancellation of the Vpoff variations (see equations 3 and 4). Still further, this choice of RL may not adequately cancel the fabrication process variations that may also cause the bias stabilization resistors (e.g., the resistors 114, 115, 118 and 119) to change.
A further problem is that the nominal value of the current I.sub.db oftentimes cannot be chosen arbitrarily. The negative voltage VGG required for operation of a circuit such as the PA may be generated by a switching inverter circuit. Switching inverter circuits generally only have a limited current sinking capability. In other words, VGG may only be able to sink a small amount of current. Consequently, the nominal value of the current I.sub.db must be selected to account for this limitation. Additionally, the variations in VGG may not be shielded enough by the bias transistor 110 if it is not biased properly in the saturation region. In that case, V.sub.B and hence the power amplifier's DC bias current I.sub.dpa varies with VGG. Thus, I.sub.dpa needs to be stabilized with respect to VGG as well.
Thus, in a multi-constraint environment, such as for a PA, the circuit from the '235 Patent may not adequately compensate for all these variations.
Therefore, it is an object of the present invention to provide a bias stabilization circuit that can adequately compensate for parameter variations such as Vpoff variations, resistance variations in bias resistors, and power supply variations.
Another object of the present invention is to provide an improved method of forming a bias stabilization circuit that can compensate for the above parameter variations.